The present disclosure relates to a semiconductor memory device and a method of manufacturing the same.
Generally, a semiconductor memory device such as Erasable Programmable Read Only Memory (EPROM) may have a multi-poly structure (in which a floating gate, an Oxide-Nitride-Oxide (ONO) layer, and a control gate are stacked). Presently, however, research is in progress on a single gate structure having advantages such as simple manufacturing processes and operation excellence.
FIG. 1 is a view illustrating a form of an applied voltage when a semiconductor memory device of a single gate structure is programmed. Hereinafter, a semiconductor memory device described below is regarded as EPROM.
The semiconductor memory device is programmed through a hot channel electron injection method. Once a program voltage +Vp is applied to N-well 10 (also serves as a control gate), a specific voltage is induced by a coupling ratio of two floating gates 20.
A voltage induced in floating gate 20 reverse an electric potential of a channel region in NMOS 30, and once a predetermined voltage VDS is applied to drain 31 of NMOS 30, a current flows from drain 31 to source 32.
Accordingly, hot channel electrons generated around a junction region of drain 31 may be injected into floating gate 20 so that a threshold voltage of NMOS 30 may become higher.
FIG. 2 is a view illustrating a form of an applied voltage when a semiconductor memory device of a typical single gate structure reads data.
Once a reading voltage +VR is applied to N-well 10, a specific voltage is induced in floating gate 20. Additionally, a positive drain voltage for a read operation is applied to drain 31 of NMOS 30 and source 32 is connected to a reference voltage. The reference voltage may include a ground (GND) or 0 Voltage, but is not limited thereto.
If electrons are injected to floating gate 20 and a threshold voltage of NMOS 30 is in a high program state, a specific voltage induced in floating gate 20 cannot turn on the NMOS so that no current flows.
Moreover, if electrons flow out from floating gate 20 and a threshold voltage of NMOS 30 is in a low erase state, a specific voltage induced in floating gate 20 turns on the NMOS so that currents flows. Thus, according to each case, data may be read.
In the semiconductor memory device of the typical single gate structure, NMOS 30 is formed so that P-well 40 where a program/read operation is performed is electrically connected to a semiconductor substrate.
Accordingly, although not shown in the drawings, a predetermined circuit device is realized in another region of the semiconductor substrate, and at this point, if the semiconductor substrate is biased to a specific negative electric potential, it may not operate.
When the semiconductor substrate is biased to a negative electric potential, in order to operate the semiconductor memory device of a single gate structure, a deep N-well separating the P-well from the semiconductor substrate may be formed.
Since the N-well 10, however, which serves as a word line of the semiconductor memory device of the single gate structure needs to be separated again from the deep N-well, it is difficult to realize the semiconductor memory device and its operations become unstable.
Furthermore, since N-well 10 serves as a control gate inducing the floating gate 20 to a specific electric potential, it needs to be separated from N-well 10 in a direction of the bit line (connected to drain 31 of NMOS 30).
Accordingly, a cell size of the semiconductor memory device becomes greater and it is difficult to apply the semiconductor memory device to a mass storage device.